1 through 15 of 259 articles found
DSP-FPGA.com 2012-13 Resource Guide
Integrating High-Level Synthesis designs into FPGA SoCs with less effort and risk
Summary:
As FPGA SoCs grow in popularity, High-Level Synthesis (HLS) tools are becoming a popular tool for hardware development, though to take advantage of their benefits designers must overcome their challenges.
As FPGA SoCs grow in popularity, High-Level Synthesis (HLS) tools are becoming a popular tool for hardware development, though to take advantage of their benefits designers must overcome their challenges.
DSP-FPGA.com 2012-13 Resource Guide
Virtual prototyping tools speed development for FPGAs with ARM-based SoC subsystems
Summary:
Software development can begin earlier with the help of virtual prototyping tools in FPGA SoCs.
Software development can begin earlier with the help of virtual prototyping tools in FPGA SoCs.
Summary:
DSP and FPGA vendors are giving embedded vision designers a boost for developing these next-gen systems thanks to image processor advancements.
DSP and FPGA vendors are giving embedded vision designers a boost for developing these next-gen systems thanks to image processor advancements.
DSP-FPGA.com 2012-13 Resource Guide
Vendors set their sights on small cells, Wi-Fi, and LTE
Summary:
Mobile World Congress 2012 saw record attendance, and the buzz was focused on small cell wireless, a peek at Wi-Fi on an Intel x86 die, and a real LTE-Advanced baseband chip demo.
Mobile World Congress 2012 saw record attendance, and the buzz was focused on small cell wireless, a peek at Wi-Fi on an Intel x86 die, and a real LTE-Advanced baseband chip demo.
DSP-FPGA.com 2012-13 Resource Guide
Boosting embedded DSP processing with open-source-based HPEC supercomputer performance
Summary:
COTS-based HPEC processing in compact, rugged deployable subsystems promises to deliver supercomputing performance in SWaP-constrained and compute-intensive embedded military applications.
COTS-based HPEC processing in compact, rugged deployable subsystems promises to deliver supercomputing performance in SWaP-constrained and compute-intensive embedded military applications.
DSP-FPGA.com 2012-13 Resource Guide
Tool providers focus on improving the efficiency of FPGA design
Summary:
As FPGAs advance, more automation will help engineers by speeding up the design process in the face of increased complexity.
As FPGAs advance, more automation will help engineers by speeding up the design process in the face of increased complexity.
Summary:
The FPGA Mezzanine Card (FMC ñ ANSI VITA 57.1) format provides a very powerful solution to high-end I/O requirements. FMCs offer a simple and straightforward, yet elegant, low-level interface. Their power comes from esch... [read more]
The FPGA Mezzanine Card (FMC ñ ANSI VITA 57.1) format provides a very powerful solution to high-end I/O requirements. FMCs offer a simple and straightforward, yet elegant, low-level interface. Their power comes from esch... [read more]
DSP-FPGA.com January 2012
Android everywhere at the 2012 International CES
Summary:
Androidís fragmentation was on display at CES, despite Googleís best efforts to generate cohesive standards, but itís not all bad.
Androidís fragmentation was on display at CES, despite Googleís best efforts to generate cohesive standards, but itís not all bad.
DSP-FPGA.com December 2011
LTE delivers on the promise of 4G, but no panacea for fragmentation
Summary:
While wireless operators add more spectrum to build their next generation networks, multimode devices will be required to adapt to an increasing number of variations in each deployment.
While wireless operators add more spectrum to build their next generation networks, multimode devices will be required to adapt to an increasing number of variations in each deployment.
Summary:
Advances in DSP development tools and chips that support both fixed- and floating-point circuitries help forge high-level design flows for FPGAs.
Advances in DSP development tools and chips that support both fixed- and floating-point circuitries help forge high-level design flows for FPGAs.
DSP-FPGA.com 2011-2012 Resource Guide
New tool for FPGA designers mitigates soft errors within synthesis
Summary:
Implementing synthesis-based mitigation offers a redux in the radiation upsets and soft errors that plague shrinking FPGA geometries.
Implementing synthesis-based mitigation offers a redux in the radiation upsets and soft errors that plague shrinking FPGA geometries.
DSP-FPGA.com 2011-2012 Resource Guide
SRIO reaches a crossroads in Intel-based DSP designs
Summary:
PCIe-to-SRIO bridges leverage Intel processors for faster, smaller, and lower power DSP designs.
PCIe-to-SRIO bridges leverage Intel processors for faster, smaller, and lower power DSP designs.
DSP-FPGA.com 2011-2012 Resource Guide
Virtual or real: Prototyping platform(s) for ARM-based FPGA design
Summary:
SoC FPGAs offer both hardware and software approaches to platform prototyping, each of which confronts different challenges of the hardware-software codesign process.
SoC FPGAs offer both hardware and software approaches to platform prototyping, each of which confronts different challenges of the hardware-software codesign process.
DSP-FPGA.com 2011-2012 Resource Guide
The small-cell base station market is getting bigger
Summary:
Will details developments and predictions in wireless processors, acquisitions, and trends spanning the final quarter of 2011 through the first half of 2012.
Will details developments and predictions in wireless processors, acquisitions, and trends spanning the final quarter of 2011 through the first half of 2012.
DSP-FPGA.com 2011-2012 Resource Guide
DSP, FPGAs, and the quest for instant gratification
Summary:
Devices integrating programmable logic into processors are easing the translation between software and hardware engineering teams in FPGA design flows.
Devices integrating programmable logic into processors are easing the translation between software and hardware engineering teams in FPGA design flows.
