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High throughput and design flexibility have positioned FPGAs as a solid silicon solution over traditional DSP devices in high-performance DSP applications like mobile base stations, medical imaging, and document imaging. In many cases, high density ASICs and DSPs appear on the same board as the FPGA. Hardware tasks, traditionally partitioned between the ASIC and FPGA, now primarily fall to FPGAs, which provide a cost-effective alternative for DSP implementation that easily can be adopted for a broad range of applications. This article tells how.
Standard-cell ASICs usually were chosen for their performance, density, complex logic designs, and cost-per-unit benefits. However, these same ASICs also increase time to market, have high development costs, and represent considerable financial risk if feature requirements change or the product doesn’t hit expected volume levels.
For example, many companies suffered significant financial setbacks developing ASICs for DSP functionality as part of the cellular base station development for the 3rd Generation Partnership Program (3GPP) standard; the culprits proved to be significant development changes in the standard as it was being established.
In addition to higher throughput and flexibility, FPGAs provide more raw data processing power than traditional DSP processors. Since FPGAs can be reconfigured in hardware, they offer complete hardware customization while implementing various DSP applications. FPGAs also boast features critical to key DSP applications, such as embedded memory, DSP blocks, and embedded processors (see Figure 1).
Figure 1. Click to zoom.
FPGAs manufactured with 90 nm technology provide up to 96 embedded DSP blocks, delivering 384 18 x 18 multipliers operating at 420 MHz. This equates to over 160 giga multiplies per second throughput – a performance improvement of over 30 times what is provided with the fastest DSPs on the market today. This configuration leaves the programmable logic elements on the FPGAs available to implement additional signal processing functions and system logic, including high-speed interfaces such as RapidIO and external memory interfaces like DDR2 controllers. With up to 8 Mb of high bandwidth embedded memory, FPGAs can eliminate the need for external memory in certain cases.
DSP development flow with structured ASICs
Structured ASICs, which represent the middle ground between FPGAs and standard-cell ASIC design solutions, are another reason developers are rethinking their use of traditional ASICs in high-performance, high-volume DSP applications. Structured ASICs deliver standard-cell ASIC-like performance and power consumption at unit costs better than FPGAs by an order of magnitude, but at very low total development costs. From a silicon perspective, they closely resemble FPGAs in terms of prefabricated base arrays with predefined logic, memory, clock networks, and I/O resources for a given device. The latest generation of structured ASICs, manufactured in 90 nm process technology, offer up to 2.2 M ASIC gates for logic and DSP, an additional 1.4 M gates dedicated for DSP Blocks, and 8.8 Mb of memory.
The same DSP development flow used to target FPGAs, including standard synthesis, verification, timing analysis, and equivalency checking tools is applicable to structured ASICs. This development flow provides system-level integration and flexibility for hardware and software partitioning of the DSP system. In addition, development tools can be combined to provide a complete design platform that allows the user to reap the benefits of performance and flexibility of a combined hardware and software implementation in a single system.
Complete DSP system design for structured ASICs requires both high-level algorithm and Hardware Description Language (HDL) development tools. The last several years has seen rapid adoption of MATLAB/Simulink-based tools targeted for FPGA and structured ASIC implementation. This integration enables system, algorithm, and hardware designers to share a common development platform, reducing time to market. Algorithmic intellectual property (IP), such as MPEG4, JPEG2000, and H.264 Video Compression and Forward Error Correction for WiMAX, has been optimized for FPGAs and structured-ASICs, enabling a further reduction in time to market.
However, if the proven original FPGA design is not used as the structured ASIC moves into high-volume production, the development process presents the same degree of risk as that of a standard-cell ASIC. To minimize risks, the design methodology must support seamless migration from the FPGA prototype to the structured ASIC (see Figure 2). Also, the system should support the FPGA with structured ASIC pin-to-pin compatibility. This eliminates re-spinning the design and schedule pressure from redeveloping and revalidating the system, resulting in significant cost savings and aforementioned time-to-market benefits.
Figure 2
Conclusion
Previously, developers were forced to use standard-cell ASICs to hit their price, space, and performance targets. In today’s market, however, increasing competitive pressures and shorter product life cycles give designers less time to develop and differentiate higher performance, and more complex designs usually requiring long verification and simulation cycles. With prices as low as $15, densities up to 2.2 M ASIC gates and 350 MHz system performance, structured ASICs offer developers a compelling alternative to standard-cell ASICs, enabling them to minimize design risk, reduce development costs, and shorten time-to-market costs across a wide variety of DSP applications.
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