As FPGA vendors strive to make their devices more SoC- and ASIC-like, they are collaborating with EDA companies to more seamlessly integrate their tools. This produces great benefits for designers as FPGA design methodologies are leading the way to new capabilities in areas such as Electronic System Level (ESL) synthesis, IP integration and re-use, and higher-level tools for software/hardware co-design.
As we approach the 50th Design Automation Conference, it's time to look back on the milestones of innovation that have happened in the EDA industry during the past five decades. Editorial Director Mike Demler lists his first five picks for the most influential developments to the EDA industry.
The International Consumer Electronics Show (CES) has expanded into an embedded electronics show in recent years with its increasing focus on electronics outside of the consumer gadget and appliance spaces. CES's showcase of electronics depends on wireless connectivity and extensive data processing, which will require more use of DSP and FPGAs.
After nearly 50 years of shrinking designs in two dimensions, extending Moore's Law to 20 nm design technology requires the use of a new technique: Double Patterning Technology (DPT). EDA vendors will see a major impact as a result, and semiconductor foundry Taiwan Semiconductor Manufacturing Corporation Limited (TSMC) recognized EDA competitors for their collaborative contributions to 20 nm design flows.
Editorial Director Mike Demler introduces EDA Digest, as well as the central "innovation" theme of its inaugural issue.
FPGAs' flexibility and configurability make them competitive the wireless infrastructure market as mobile backhaul ramps up to free up wireless spectrum for the growing population of data-hungry mobile devices.
A rapid development pace for FPGA innovation might spell a fast approach to the end of Moore's Law, but FPGA users will continue to see performance and functionality increases.
The upcoming high-performance microprocessor and IC show is holding events that are "must-see"s for FPGA and DSP designers, including sessions on OpenCL, 3D IC technology, another round of ASICs vs FPGAs, embedded vision, and DSP's role in the future of wireless networking.
After the recent introduction of several new standards for interfaces between FPGA-based motherboards and add-on daughter cards to the FPGA industry, FPGA add-on product manufacturers have contributed new products that demonstrate the diversity of applications the new standards have enabled.
The proliferation of design tools by FPGA and EDA vendors is giving designers more choice in hardware/software, virtual/real platforms.
ASIC development costs are rising, which make FPGAs an attractive and advantageous alternative - in some cases.
As FPGAs advance, more automation will help engineers by speeding up the design process in the face of increased complexity.
Android’s fragmentation was on display at CES, despite Google’s best efforts to generate cohesive standards, but it’s not all bad.
While wireless operators add more spectrum to build their next generation networks, multimode devices will be required to adapt to an increasing number of variations in each deployment.
Devices integrating programmable logic into processors are easing the translation between software and hardware engineering teams in FPGA design flows.
FPGAs can offer designers a cost-performance advantage over ASICs for applications that require leading-edge semiconductor processes, but improvements in design tools and ease-of-use will be required in order to gain more widespread adoption.
The merger and acquisition game relating to EDA companies has changed, with IC design tools becoming a valuable addition to non-EDA companies with plans to develop more highly integrated solutions for electronic product development.
New alliance sees Microsoft Kinect, smart cameras, algorithms and processors as the future of input devices.
Xilinx defies Moore’s Law and increasing fab costs by implementing stacked chip FPGAs. This might be a game-changer.
Software is key to Intel's DSP plans.