HILLSBORO, OR – FEBRUARY 19, 2008 – Lattice Semiconductor today announced that registration is now open for its latestwebcast, “Interfacing Texas Instruments’ High Sample Rate ADCs to FPGAs,” scheduled for Wednesday, February 27, 11:00 AM Pacific/2:00 PM Eastern.

Systems migrating to higher sample rate/ resolution ADCs often require an FPGA[] with an interface speed of approximately 800 Mbps to bridge between existing hardware and the newer interface provided by the higher speed ADC. Previously, only more expensive, high-end FPGAs could satisfy this requirement. Now, the LatticeECP2/M FPGA family is able to provide these bridge functions in an optimally sized FPGA at a significantly lower cost. With the LatticeECP2/M FPGA devices, designers can focus on processing the ADC data within the FPGA and routing it to other parts of their system without having to worry about the timing details of high-speed ADC interfaces.

This webcast will examine the timing challenges and design details of a deserializer logic implementation within an FPGA fabric, and will provides the details of a modified implementation that meets all the timing requirements.

For more information and to register for the webcast, please visit www.latticesemi.com/corporate/webcasts/interfac[...]$3F$0F$3