Library Now Includes All Cortex Processors, AMBA AXI Fabric, Periphe

HILLSBORO, OR – NOVEMBER 23, 2009 – Lattice Semiconductor Corporation (NASDAQ: LSCC) and Praesum Communications today announced the availability of the Serial RapidIO 2.1 endpoint soft IP core for the LatticeECP3(tm) FPGA[] family. The core supports 1x, 2x and 4x lane configurations at up to 3.125Gbps lane speeds, offering the lowest cost, lowest power programmable SRIO solution in the industry. Lattice also announced that it has licensed this IP core from Praesum and has full rights to use and sub-license the Serial RapidIO IP core.

Panel to discuss issues that arise when time-to-market and cost reductions dominate IP design and integration, since instituting design practices for enhanced quality can be seen as overhead by engineers and engineering managers

Scalable processor architecture provides lowest cost yet versatile and feature-rich solution that will secure customers’ design investments across a range of embedded applications.

MIPS Technologies Licenses MIPS32(r) Architecture to Altera Corporation

MIPS Technologies Licenses MIPS32(r) Architecture to Altera Corporation

Silicon vendor independence achieved for high throughput FFT IP

New IP core converts interlaced to progressive video for display, H.264 encoding, or other processing.

As an IP business catalyst company D&R offers to IP providers an advanced turnkey Web solution based on a decade of research for publishing, marketing, packaging and delivering their IPs or products to the market.

Key industry leaders and visionaries will discuss the IP challenges facing innovative teams across engineering, R&D, supply-chain and legal departments on a daily basis, outlining different methods for reducing risk in R&D project selection and for building IP portfolios that generate higher profits and licensing revenues, protect business unit profits from competition, and contain costs.

Digital Core Design (DCD) today releases World’s smallest and fastest 8051 core. The 7150 ASIC gates for complete system including 8051-CPU, full duplex UART, Timers 0&1, Advanced Power Management Unit, eight I/O lines, eight external interrupts INT0-INT7 and 2-wire DoCD on-chip debugger is the best achievement on the IP Market. DT8051 runs Dhrystone 2.1 benchmark program 8.1 times faster than the original 80C51 at the same frequency.

Digital Core Design (DCD) today releases the 5th generation of World’s fastest and most popular 8051 core. DP8051 runs Dhrystone 2.1 benchmark program 11.45 to 14.74 times faster than the original 80C51 at the same frequency.

SUPI4 protocol chip, presented by Phoenix Contact at SPS/IPC Drives 2008, is an implementation of the Interbus-IP core

Altera Corporation (NASDAQ: ALTR) today announced silicon availability of the industry’s highest density transceiver FPGA[].